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The instruction unit (IU) in a central processing unit (CPU) is responsible for organising program instructions to be fetched from memory, and executed, in an appropriate order. It is a part of the control unit, which in turn is part of the CPU. In the simplest style of computer architecture, the instruction cycle is very rigid, and runs exactly as specified by the programmer. In the Instruction Fetch part of the cycle, the contents of the program counter (PC) register are placed on the address bus, and sent to the memory unit; the memory unit returns the instruction at that address, and it is latched into the Instruction Register (IR); and the contents of the PC are incremented or over-written by a new value (in the case of a Jump or Branch instruction) ready for the next instruction cycle. This becomes a lot more complicated, though, once performance-enhancing features are added, such as instruction pipelining, out-of-order execution, and even just the introduction of a simple instruction cache.〔John L. Hennessy and David A. Patterson (1990), ''Computer Architecture: a quantitative approach'', Morgan Kaufmann Publishers, Palo Alto, USA, ISBN 1-55860-069-8〕 ==See also== *Branch prediction and the Branch prediction buffer * *Branch target predictor and the Branch target buffer * *Branch delay slot *Instruction scheduling * *Instruction selection * *Data dependency or Data hazard * *Scoreboarding *Very long instruction word (VLIW) *Superscalar processor *Instruction prefetch buffer and Instruction issue *Opcode *Analysis of Instruction parallelism, Instruction frequencies, Instruction mix * *Instruction path length or Instruction count 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「instruction unit」の詳細全文を読む スポンサード リンク
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